1. Field of the Invention
The present invention relates to chemical mechanical planarization in the production of semiconductor devices. More particularly, the present invention relates a novel method of aiding planarization by wetting surfaces of device materials to be planarized.
2. State of the Art
In the fabrication of integrated circuits, it is often necessary to planarize layered materials which are placed on a semiconductor substrate during the formation of the intergrated circuits. This planarization is used to remove topography, surface defects, scratches, roughness, or embedded particles in the material layers. One of the most widely utilized planarization processes is chemical mechanical planarization (hereinafter "CMP"). The CMP process involves holding and rotating the semiconductor substrate while bringing the material layer on the semiconductor substrate to be planarized against a wetted planarizing surface under controlled chemical, pressure, and temperature conditions. FIGS. 6 and 7 show an exemplary CMP apparatus 200 having a rotatable planarizing platen 202 and a planarizing pad 204 mounted to the planarizing platen 202. A rotatable substrate carrier 206 is adapted so that a force, usually between about 0.5 and 9.0 pounds per square inch, indicated by arrow 208 is exerted on a material layer (not shown) on a semiconductor substrate 210 (shown in FIG. 7). The semiconductor substrate 210 can be held in place on the rotatable substrate carrier 206 by well-known techniques including mechanical affixation, vacuum affixation, friction affixation, and the like.
The rotatable substrate carrier 206 is rotated in direction 212 by a carrier rotation mechanism 214, such as a motor or the like, at between about 0 and 100 revolutions per minute. The planarizing platen 202 and planarizing pad 204 are rotated in direction 216 by a platen rotating mechanism 218, such as a motor or the like, at between about 10 and 100 revolutions per minute. If the planarizing platen 202 and planarizing pad 204 are rotated at the same velocity as the rotational velocity of the rotatable substrate carrier 206, the average velocity is the same at every point on the semiconductor substrate 210.
A chemical slurry 220 (shown in FIG. 6) is supplied through a conduit 222 which dispenses the chemical slurry 220 onto the planarizing pad 204. The chemical slurry 220 contains a planarizing agent, such as alumina, silica, or fumed silica carried in an ammonium hydroxide solution or the like, which is used as the abrasive material for planarization. Additionally, the chemical slurry 220 may contain selected chemicals which etch various surfaces of the material layer of the semiconductor substrate 210 during the planarization.
One example of a semiconductor device, fabrication of which requires planarization steps, is a DRAM (Dynamic Random Access Memory) chip. A widely-utilized DRAM chip manufacturing process utilizes CMOS (Complementary Metal Oxide Semiconductor) technology to produce DRAM circuits which comprise an array of unit memory cells, each including one capacitor and one transistor, such as a field effect transistor ("FET"). In the most common circuit designs, one side of the transistor is connected to external circuit lines called the bit line and the word line, and the other side of the capacitor is connected to a reference voltage that is typically one-half the internal circuit voltage. In such memory cells, an electrical signal charge is stored in a storage node of the capacitor connected to the transistor which charges and discharges circuit lines of the capacitor.
FIGS. 8-18 illustrate an exemplary method of fabricating a capacitor for a CMOS DRAM memory cell, as set forth in commonly-owned U.S. Pat. No. 5,162,248, issued Nov. 10, 1992 to Dennison et al., hereby incorporated herein by reference. It should be understood that the figures presented in conjunction with this description are not meant to be actual cross-sectional views of any particular portion of an actual semiconductor device, but are merely idealized representations which are employed to more clearly and fully depict the process than would otherwise be possible.
FIG. 8 illustrates an intermediate structure 300 in the production of a memory cell. This intermediate structure 300 comprises a semiconductor substrate 302, such as a lightly doped P-type crystal silicon substrate, which has been oxidized to form thick field oxide areas 304 and exposed to implantation processes to form drain regions 306 and source regions 308. Transistor gate members 310 are formed on the surface of the semiconductor substrate 302, including the gate members 310 residing on a substrate active area 312 spanned between the drain regions 306 and the source regions 308. The transistor gate members 310 each comprise a lower buffer layer 314, preferably silicon dioxide, separating a gate conducting layer or wordline 316 of the transistor gate member 310 from the semiconductor substrate 302. Transistor insulating spacer members 318, preferably silicon dioxide or silicon nitride, are formed on either side of each transistor gate member 310 and a cap insulator 320, also preferably silicon dioxide or silicon nitride, is formed on the top of each transistor gate member 310.
A first barrier layer 322, generally tetraethyl orthosilicate--TEOS, is disposed over the semiconductor substrate 302, the thick field oxide areas 304, and the transistor gate members 310. A second barrier layer 324 (generally made of borophosphosilicate glass--BPSG, phosphosilicate glass--PSG, or the like) is deposited over the first barrier layer 322.
As shown in FIG. 9, a resist material 326 is patterned on the second barrier layer 324, such that predetermined areas for subsequent memory cell capacitor formation will be etched. The second barrier layer 324 and the first barrier layer 322 are etched to form vias 328 to expose the drain regions 306 on the semiconductor substrate 302, as shown in FIG. 10. The resist material 326 is then removed, as shown in FIG. 11, and a conformal layer of first conductive material 330, generally a doped polysilicon, is then applied over second barrier layer 324, preferably by sputtering or chemical vapor deposition, as shown in FIG. 12. The first conductive material layer 330 makes contact with each drain region 306 of the semiconductor substrate 302.
As shown in FIG. 13, a thick layer of resist material 332 is deposited over the first conductive material 330. The thick resist material 332 should be sufficiently thick enough to fill the first conductive material 330 lined vias 328. The thick resist material 332 is removed down to the first conductive material 330 by CMP, as shown in FIG. 14.
As shown in FIG. 15, the upper portions (planar to the substrate) of the first conductive material 330 are removed, generally by wet etch or an optimized CMP etch, to separate neighboring first conductive material 330 structures, thereby forming individual cell containers 334 residing in the vias 328 and exposing the second barrier layer 324. It can be seen that the thick layer of resist material 332 protects the first conductor material 330 during the formation of the individual cell containers 334. The thick resist layer 332 is then removed, generally by an etch, which also removes a portion of the second barrier layer 324, as shown in FIG. 16.
A dielectric material layer 336 is deposited over the cell container 334 and the exposed areas of the second barrier layer 324, as shown in FIG. 17. A second conductive material layer 338 is then deposited over the dielectric material layer 336, as shown in FIG. 18, which serves as a capacitor cell plate common to an entire array of capacitors.
One processing problem in the use of CMP as a planarization technique to remove the thick resist material 332 down to the first conductive material 330, as shown in FIG. 14, stems from the hydrophobic nature of both the thick resist material 332 and the non-porous planarizing pads 204 (see FIGS. 6 and 7) used in the CMP process. Planarizing pads are usually composed of either a matrix of cast polyurethane foam with filler material to control hardness or polyurethane impregnated felts. Polyurethane is utilized because urethane chemistry allows the pad characteristics to be tailored to meet specific mechanical properties. Non-porous planarizing pads 204 are advantageous for planarization because they have good pad to pad repeatability (similar removal characteristics for similar pads) and uniformity of planarization. However, upon initial contact of the non-porous planarizing pad 204 and the thick resist material 332, the surfaces of each "de-wet", resulting in an initial stiction which can literally pop the semiconductor substrate 210 (see FIG. 7) from the rotatable substrate carrier 206. This may occur regardless of technique (i.e., mechanical affixation, vacuum affixation, friction affixation, and the like) used to retain the semiconductor substrate 210 on the rotatable planarizing platen 202. This may occur even when the rotatable substrate carrier 206 has a recess to receive the semiconductor substrate 210 because the force pulling the semiconductor substrate 210 toward the planarizing pad 204 is substantially greater than the force keeping the semiconductor substrate 210 in the recess of the rotatable substrate carrier 206. Furthermore, when the surfaces de-wet (assuming that the semiconductor substrate 210 does not pop out of the substrate carrier 206), no polishing occurs.
In order to overcome this problem, the present inventors have succeeded in using a two-step process, wherein the resist is first planarized with a porous planarizing pad, such as an IC-1000 pad from Rodel, Inc. of Newark, Del., which does not appear to suffer from this de-wetting to the same degree as non-porous pads. The planarizing is then completed with a non-porous pad, leaving the containers full of resist, but the bulk of the surface is hydrophillic due to the fact that the underlying layer is now exposed. However, utilizing a two-step process is time consuming and thus increases the cost of the semiconductor component.
Therefore, it would be desirable to develop a technique to reduce de-wetting between the planarizing pad and the semiconductor substrate using commercially-available, widely-practiced semiconductor device fabrication techniques without requiring additional processing steps.